Vision VHD-800 Specifikace stáhnout pdf (Strana 6)

Note: Although the command compile is still known by the SYNOPSYS DESIGN COMPILER, it has been re-

placed by compile_ultra. During this exercise, you may ﬁnd the compile command somewhere, but this is

for demonstration purposes only.

4.5 The Sample Design

Now that you are familiar with the most important synthesis steps, we will explain how to use the SYNOPSYS DESIGN

COMPILER with the aid of a small sample design. Open the ﬁle ./sourcecode/crc4.vhd and have a look at the source. Make

sure you understand the design.

Start analyzing the design by selecting File→Analyze... in the Design Vision GUI. Press ADD... and in the pop-up

window select the ﬁle crc4.vhd. As library select WORK . You can tick the ﬁeld Create new library if it doesn‘t exist. Click

OK to initiate the analyze step. You will not see any design in the Hierarchy Browser window as this command only checks

the syntax.

After having translated the VHDL source code, the next step in the SYNOPSYS DESIGN COMPILER synthesis ﬂow is to build

a technology independent netlist, implementing the described behavior by means of generic circuit elements. Perform the

following steps in order to start the elaboration:

1. Navigate to File→Elaborate...

2. Select Library: WORK

3. Select Design: CRC4(BEHAVE CRC4)

4. Select Reanalyze out-of-date libraries

5. Click OK

You should now see an icon for crc4 in the Hierarchy Browser, indicating that the design is now present in SYNOPSYS

DESIGN COMPILER’s memory.

It is good practice to store your design after every important step in the synthesis ﬂow. This eases potential re-iteration

steps. Select File→Save as... and change to the ./DDC directory in the Save Design dialog box that pops up. Save

the design in ∗.ddc format to a ﬁle named crc4.ddc.

Now, let us start mapping the circuit to the target library, i.e., perform the compilation step. Navigate to Design→\

Compile Design.... In the following pop-up window click the OK button to start the compilation of your design.

When the compilation ﬁnishes, the next step within the design ﬂow is to make your design ready for further use in other

EDA tools. For that, you will now create a Verilog netlist from your design (which can later be read from other EDA tools).

In order to save your design as a Verilog netlist, you must ﬁrst perform a simple conversion to adapt the internal SYNOPSYS

DESIGN COMPILER name deﬁnitions to standard Verilog deﬁnitions. Enter the following commands into the Design Vision

Console in order to perform the conversion:

dvc > change_names -rule verilog -hierarchy

Afterwards, navigate to File→Save As..., select the netlists directory and enter the name crc4. Choose the format

VERILOG (v) and press SAVE. The netlist (crc4.v) is now ready for back-end design.

4.5.1 The Netlist

The Verilog netlist, which you have just created in the previous task, is a very widely accepted data format (i.e., can be read

by most of the CAE/CAD tools available on the market). Therefore, we will investigate it a little bit more in detail throughout

this section.

Student Task 1:

• All synthesis-related ﬁles can be found in the directory synopsys. Therefore, use a UNIX shell and change to

that directory ﬁrst:

sh > cd synopsys

• Next, navigate to the previously created netlist (If you have followed our instructions, it should be located in

./synopsys/netlists/).

1 2 3 4 5 6 7 8 9 10 11 ... 19 20

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