Vision VHD-800 Specifikace stáhnout pdf (Strana 16)

6.5 Setting Input Drivers and Output Load

Input Drivers: In the next steps we want to investigate how the driver that drives the inputs of our circuit can affect the

overall timing. Until now the SYNOPSYS DESIGN COMPILER assumed ideal input signals that have inﬁnitely steep edges.

In reality, our inputs are driven by the outputs of some other circuit with limited driving capabilities. That is, the edges of the

input signals to our design have ﬁnite ramp (rise and fall) times greater than zero and which depend on the input driver’s

strength.

Student Task 12:

• First, restart from scratch and compile the design, using the same constraints as before (A period of 1 ns, input

and output delays of 0.4 ns).

• Furthermore, let us add a driving cell constraint. Specify that all inputs of our circuit are being driven by a cell

that is equivalent in driving capability to the BUFM4W -cell (Hint: man set_driving_cell).

The following example describes the syntax of this command (To gather information about the library name,

have a look at the link command.):

dcs > set_driving_cell -library <library_name> -lib_cell <cell_name> -pin \

<pin_name> [all_inputs]

• Investigate the timing information now.

slack

= slack

= A =

slack

= slack

• What is the effect on the timing and on the area of the design (without compiling)?

Output Load: The propagation delay of a CMOS circuit depends also on the capacitive load it is driving at the outputs.

Basically, the more capacitance a gate has to drive, the longer it will take to charge (or discharge) the load capacitance.

At the moment we have not speciﬁed what is connected to the outputs of our circuit. Thus, the SYNOPSYS DESIGN

COMPILER assumes that there is no load connected to the outputs (i.e., the capacitance is equal to 0 F). But exactly that

may affect the timing considerably. Let us examine how much the output load can inﬂuence the timing.

Go on with the design from the previous task and use it as a starting point for this task. Have a look at the cell names

within one of the timing reports (e.g., ND2M2W , XOR2M2WA, etc.). The cell driving strength index is given by the digits

following the M character in the name of the standard cell. Depending on the cell, it ranges from 0 up to 48. For further

details, refer to the standard cell databook located in ./docs/stdcell low vt b03 databook.pdf. You will discover relatively low

drive gates at the outputs (e.g., ND2M2W).

Currently, there is no load connected to the outputs. Now, add a load corresponding to four times the load of the input

pin of the cell BUF1 to every output of the design (Hint: man set_load, man load_of). The following command is an

example and sets the load of all outputs equal to eight times the load of a BUFM4W:

dcs > set_load [expr 8

[load_of uk65lscllmvbbl_120c25_tc/BUFM4W/A]] [all_outputs]

Until now we have not modiﬁed the netlist, we have just changed the boundary conditions. It is possible to analyze

the timing under these conditions (without compiling a second time). If the SYNOPSYS DESIGN COMPILER knows about

the input driver and the output load ”in advance”, it is able (or at least it tries) to synthesize a netlist that can meet the

requirements. Therefore, these constraints should be added prior to compilation.

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